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ORCIDIntegration, Volume 46
Volume 46, Number 1, January 2013
- Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang:
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. 1-9 - David Cuesta, José Luis Risco-Martín
, José L. Ayala, José Ignacio Hidalgo:
3D thermal-aware floorplanner using a MOEA approximation. 10-21 - Sina Basir-Kazeruni, Hao Yu, Fang Gong, Yu Hu, Chunchen Liu, Lei He:
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. 22-32 - Francesco Zanini, David Atienza, Giovanni De Micheli:
A combined sensor placement and convex optimization approach for thermal management in 3D-MPSoC with liquid cooling. 33-43
- Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan, Kevin Skadron:
Architectural implications of spatial thermal filtering. 44-56 - Hanhua Qian, Chip-Hong Chang, Hao Yu:
An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits. 57-68
- Sherief Reda, Abdullah Nazma Nowroz, Ryan Cochran, Stefan Angelevski:
Post-silicon power mapping techniques for integrated circuits. 69-79 - Zhigang Hao, Sheldon X.-D. Tan, Guoyong Shi:
Statistical full-chip total power estimation considering spatially correlated process variations. 80-88
Volume 46, Number 2, March 2013
- Carlos González, Sergio Sánchez, Abel Paz, Javier Resano, Daniel Mozos, Antonio Plaza:
Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing. 89-103 - Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez:
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. 104-118 - Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida:
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. 119-130 - Kanad Basu, Chetan Murthy, Prabhat Mishra:
Bitmask aware compression of NISC control words. 131-141 - Wenxu Sheng, Sheqin Dong:
Multi-bend bus-driven floorplanning considering fixed-outline constraints. 142-152 - Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng:
Post-routing layer assignment for double patterning with timing critical paths consideration. 153-164 - Alireza Saberkari, Eduard Alarcón, Shahriar B. Shokouhi:
Fast transient current-steering CMOS LDO regulator based on current feedback amplifier. 165-171 - Ramy Iskander, Marie-Minerve Louërat, Andreas Kaiser:
Hierarchical sizing and biasing of analog firm intellectual properties. 172-188 - Aliakbar Niknafs, Majid Mohammadi:
Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares. 189-196 - José Luis Imaña, Román Hermida, Francisco Tirado:
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials. 197-210 - Ali Zakerolhosseini, Morteza Nikooghadam:
Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m). 211-217
Volume 46, Number 3, June 2013
- Nadia Nedjah, Luiza de Macedo Mourelle:
Hardware for bioinformatics applications. 219 - Marcos Santana Farias, Nadia Nedjah, Luiza de Macedo Mourelle:
Hardware implementation of subtractive clustering for radionuclide identification. 220-229 - Agathoklis Papadopoulos, Ioannis Kirmitzoglou, Vasilis J. Promponas, Theocharis Theocharides:
FPGA-based hardware acceleration for local complexity analysis of massive genomic data. 230-239 - Edgar J. Garcia Neto Segundo, Nadia Nedjah, Luiza de Macedo Mourelle:
A scalable parallel reconfigurable hardware architecture for DNA matching. 240-246
- Farshad Moradi, Tuan Vu Cao, Elena I. Vatajelu, Ali Peiravi, Hamid Mahmoodi, Dag T. Wisland:
Domino logic designs for high-performance and leakage-tolerant applications. 247-254 - Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor:
A formal framework for interfacing mixed-timing systems. 255-264 - Isidoros Sideris, Kiamal Z. Pekmestzi:
A column parity based fault detection mechanism for FIFO buffers. 265-279 - Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih:
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs. 280-289 - Zhi-Wei Chen, Jin-Tai Yan:
Routability-constrained multi-bit flip-flop construction for clock power reduction. 290-300 - Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
An efficient method for gradient-aware dummy fill synthesis. 301-309 - Antara Ain, Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay:
Post-silicon debugging of PMU integration errors using behavioral models. 310-321
Volume 46, Number 4, September 2013
- Tao Wu, Shuguo Li, Litian Liu:
Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications. 323-332 - Nabihah Ahmad, S. M. Rezaul Hasan:
Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate. 333-344 - Kenichi Shinkai, Masanori Hashimoto, Takao Onoye:
A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations. 345-358 - Jiangpeng Li, Jun Ma, Guanghui He:
A memory efficient parallel layered QC-LDPC decoder for CMMB systems. 359-368 - Po-Hsun Wu, Tsung-Yi Ho:
Bus-driven floorplanning with thermal consideration. 369-381 - Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. 382-391 - Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng:
SmipRef: An efficient method for multi-domain clock skew scheduling. 392-403 - Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki:
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme. 404-412 - Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani:
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs. 413-426 - Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Solution of PDEs-electrically coupled systems with electrical analogy. 427-440 - Enrique López-Morillo, Fernando Muñoz, Antonio Torralba, Fernando J. Marquez, I. Rebollo, José Ramón García Oya:
Compact low-power implementation for continuous-time ΣΔ modulators. 441-448 - Samiran Dam, Pradip Mandal:
Modeling and design of CMOS analog circuits through hierarchical abstraction. 449-462
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