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ORCID9th MEMOCODE 2011: Cambridge, UK
- Satnam Singh, Barbara Jobstmann, Michael Kishinevsky, Jens Brandt:
9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, UK, 11-13 July, 2011. IEEE 2011, ISBN 978-1-4577-0117-7
Session 1: Modeling and Implementation of Software-Hardware Systems
- David J. Greaves, Satnam Singh:
Distributing C# methods and threads over Ethernet-connected FPGAs using Kiwi. 1-9 - Paraskevas Bourgos, Ananda Basu, Marius Bozga, Saddek Bensalem, Joseph Sifakis, Kai Huang:
Rigorous system level modeling and analysis of mixed HW/SW systems. 11-20
Session 2: Synthesis Techniques
- Huafeng Yu
, Jean-Pierre Talpin, Loïc Besnard, Thierry Gautier, Hervé Marchand, Paul Le Guernic:
Polychronous controller synthesis from MARTE CCSL timing specifications. 21-30 - Georg Hofferek, Roderick Bloem:
Controller synthesis for pipelined circuits using uninterpreted functions. 31-42 - Wenchao Li, Lili Dworkin, Sanjit A. Seshia:
Mining assumptions for synthesis. 43-50
Session 3: Transformation and Refinement Techniques
- Andrey Mokhov, Danil Sokolov, Maxim Rykunov, Alex Yakovlev:
Formal modelling and transformations of processor instruction sets. 51-60 - Nirav Dave, Michael Katelman, Myron King, Arvind, José Meseguer:
Verification of microarchitectural refinements in rule-based systems. 61-71
Design Contest
- Derek Chiou:
MEMOCODE 2011 Hardware/Software CoDesign Contest: NoC simulator. 73-76 - Michael Papamichael:
Fast scalable FPGA-based Network-on-Chip simulation models. 77-82 - Mahdy Zolghadr, Koosha Mirhosseini, Saeid Gorgin, Abbas Nayebi:
GPU-based NoC simulator. 83-88
Invited Talk 2
- Anna Slobodová, Jared Davis, Sol Swords, Warren A. Hunt Jr.:
A flexible formal verification framework for industrial scale validation. 89-97
Session 4: Verification Problems
- Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta:
Predictive analysis for detecting serializability violations through Trace Segmentation. 99-108 - Bijoy Antony Jose, Abdoulaye Gamatié, Julien Ouy, Sandeep K. Shukla:
SMT based false causal loop detection during code synthesis from Polychronous specifications. 109-118 - Saddek Bensalem, Andreas Griesmayer, Axel Legay, Thanh-Hung Nguyen, Doron A. Peled:
Efficient deadlock detection for concurrent systems. 119-129
Invited Tutorial 2
- Dan R. Ghica:
Function interface models for hardware compilation. 131-142
Invited Tutorial 3
- Christopher Jefferson:
Modern constraint solving by propagation. 143
Invited Talk 3
- Mark Shand:
A case study of hardware software co-design in a consumer ASIC. 145-150
Session 5: Verification and Simulation Techniques
- Ralf Wimmer, Ernst Moritz Hahn, Holger Hermanns, Bernd Becker:
Reachability analysis for incomplete networks of Markov decision processes. 151-160 - Paula Herber, Marcel Pockrandt, Sabine Glesner:
Transforming SystemC Transaction Level Models into UPPAAL timed automata. 161-170 - Giovanni Funchal, Matthieu Moy:
Modeling of time in discrete-event simulation of systems-on-chip. 171-180
Session 6: Testing, Debug, and Assertion-based Validation
- Daniel Schwartz-Narbonne, Feng Liu, Tarun Pondicherry, David I. August, Sharad Malik:
Parallel assertions for debugging parallel programs. 181-190 - Lingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan:
Automatic generation of assertions from system level design using data mining. 191-200 - Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli, Stefano Soffia:
EFSM-based model-driven approach to concolic testing of system-level design. 201-209
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