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ORCIDISVLSI 2018: Hong Kong, China
- 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-7099-6
Session 01: Analog and Mixed Signal I
- Lakshmi Nediyara Suresh
, Bhaskar Manickam:
Gyrator-C Based Bandpass Filter with Improved Dynamic Range for Fully Integrated RF Front-End. 1-5 - Yang Nan, Chenchang Zhan, Guanhua Wang, Linjun He, Han Li:
Replica-Based Low Drop-Out Voltage Regulator with Assistant Power Transistors for Digital VLSI Systems. 6-9 - Vikas Rana:
Area Efficient NMOS Based Positive and Negative Voltage Multiplier. 10-15
Session 02: Digital Circuits and FPGA based Design I
- Fanglei Hu, Min Zhang, Hailong Jiao:
Achieving Low Power Classification with Classifier Ensemble. 16-21 - Jinhang Choi, Srivatsa Rangachar Srinivasa, Yasuki Tanabe, Jack Sampson, Vijaykrishnan Narayanan:
A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs. 22-27 - Zhe Li, Ji Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic Computing. 28-33
Session 03: Testing, Reliability, and Fault-Tolerance I
- Xiaobang Liu, Ranga Vemuri:
Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon Validation. 34-39 - Sukanta Dey, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi:
PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution. 40-45 - Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh:
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. 46-51
Session 04: Computer Aided Design and Verification I
- Somayeh Kashi, Ahmad Patooghy, Dara Rahmatiy, Mahdi Fazeli, Michel A. Kinsy:
Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach. 52-57 - Leslie Hwang, Beomjin Kwon, Martin D. F. Wong:
Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs. 58-63 - Yu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang, Rung-Bin Lin:
Designing and Benchmarking of Double-Row Height Standard Cells. 64-69
Session 05: Emerging and Post-CMOS Technologies I
- Dongqin Zhou, Keni Qiu, Yuanchao Xu, Xin Shi, Yongpan Liu:
A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors. 70-75 - Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Peng Yang, Zhehui Wang, Luan H. K. Duong:
A Comprehensive Electro-Optical Model for Silicon Photonic Switches. 76-81 - Jan Nevoral, Richard Ruzicka, Václav Simek:
CMOS Gates with Second Function. 82-87
Session 06: System Design and Security I
- S. R. Swamy Saranam, Madhu Mutyam:
TDC: Tagless DRAM Cache. 88-93 - Haeyoon Cho, Joonho Kong, Arslan Munir, Naresh Kumar Giri:
CT-Cache: Compressed Tag-Driven Cache Architecture. 94-99 - Sri Harsha Gade, Hemanta Kumar Mondal, Sujay Deb:
High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless Links. 100-105
Special Session 01: Shall We Jointly Address VLSI Reliability and Security?
- Qiaoyan Yu, Zhiming Zhang, Jaya Dofe:
Investigating Reliability and Security of Integrated Circuits and Systems. 106-111 - Patrick Cronin, Chengmo Yang, Yongpan Liu:
Reliability and Security in Non-volatile Processors, Two Sides of the Same Coin. 112-117 - Lake Bu, Miguel Mark, Michel A. Kinsy:
A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs. 118-123 - Senwen Kan, Jennifer Dworak:
Can Soft Errors be Handled Securely? 124-129
Session 07: System Design and Security II
- Zhezhi He, Shaahin Angizi, Adnan Siraj Rakin, Deliang Fan:
BD-NET: A Multiplication-Less DNN with Binarized Depthwise Separable Convolution. 130-135 - Yingjian Ling, Kan Zhong, Yunsong Wu, Duo Liu, Jinting Ren, Renping Liu, Moming Duan, Weichen Liu, Liang Liang:
TaiJiNet: Towards Partial Binarized Convolutional Neural Network for Embedded Systems. 136-141 - Zihao Liu, Tao Liu, Jie Guo, Nansong Wu, Wujie Wen:
An ECC-Free MLC STT-RAM Based Approximate Memory Design for Multimedia Applications. 142-147 - Kai Yang, Jungmin Park, Mark Tehranipoor, Swarup Bhunia:
Robust Timing Attack Countermeasure on Virtual Hardware. 148-153
Special Session 02: Emerging Computing and Memory Technologies at Post-CMOS Era
- Meng Yang, Bingzhe Li, David J. Lilja, Bo Yuan, Weikang Qian:
Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic Computing. 154-159
Poster Session
- Han Li, Chenchang Zhan, Ning Zhang:
Fully-on-Chip Digitally Assisted LDO Regulator with Improved Regulation and Transient Responses. 160-163 - Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni:
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. 164-169 - Harsha M. V., B. P. Harish:
An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation. 170-174 - Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra:
Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS. 175-180 - Jalaja S, Vijaya Prakash A. M:
Design of Low Power SAR ADC Using Clock Retiming. 181-186 - Koichiro Ishibashi, Shiho Takahashi:
A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT Sensors. 187-190 - Karen Khachikyan, Abraham Balabanyan, Hrachya Gumroyan:
Precise Duty Cycle Variation Detection and Self-Calibration System for High-Speed Data Links. 191-196 - Changcheng Tang, Zuochang Ye, Yan Wang:
Parametric Circuit Optimization with Reinforcement Learning. 197-202 - Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli:
End-to-End Industrial Study of Retiming. 203-208 - Kalindu Herath, Alok Prakash, Udaree Kanewala, Thambipillai Srikanthan:
Communication-Aware Module Placement for Power Reduction in Large FPGA Designs. 209-214 - Qian Chen, Sheqin Dong:
A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm. 215-219 - Tomás Grimm, Djones Lettnin, Michael Hübner:
ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification. 220-225 - Mohammad Baharloo, Ahmad Khonsari, Pouya Shiri, Iman Namdari, Dara Rahmati:
High-Average and Guaranteed Performance for Wireless Networks-on-Chip Architectures. 226-231 - Lei Rao, Bin Zhang, Jizhong Zhao:
Hardware Implementation of Reconfigurable Separable Convolution. 232-237 - Xinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, Chun Jason Xue, Jingtong Hu:
Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs. 238-244 - Md Jubaer Hossain Pantho, Pankaj Bhowmik, Christophe Bobda:
Pixel-Parallel Architecture for Neuromorphic Smart Image Sensor with Visual Attention. 245-250 - Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal, Anupam Chattopadhyay:
Lightweight ASIC Implementation of AEGIS-128. 251-256 - Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang:
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. 257-262 - Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao:
MRAM-on-FDSOI Integration: A Bit-Cell Perspective. 263-268 - Subhendu Kumar Sahoo, Krishna Dhoot, Rasmita Sahoo:
High Performance Ternary Multiplier Using CNTFET. 269-274 - Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao:
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. 275-280 - Ankita Porwal, Chitrakant Sahu:
Biosensing Performance Optimization of DMFET for Fully Filled and Partially Filled Cavity. 281-286 - Suraj Paul, Navonil Chatterjee, Prasun Ghosal:
A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults. 287-292 - Subrata Das, Debesh Kumar Das:
Floorplanning in Graphene Nanoribbon (GNR) Based Circuits. 293-298 - Cunxi Yu, Heinz Riener, Francesca Stradolini, Giovanni De Micheli:
Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model. 299-304 - Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits. 305-310 - Mahmoud A. Elmohr, Sachin Kumar, Mustafa Khairallah, Anupam Chattopadhyay:
A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption. 311-315 - Ajinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi:
0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR. 316-320 - Soroush Khaleghi, Wenjing Rao:
Hardware Obfuscation Using Strong PUFs. 321-326 - Yunxi Guo, Timothy Dee, Akhilesh Tyagi:
Multi-block APUF with 2-Level Voltage Supply. 327-332 - Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao:
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. 333-338 - Xin Shi, Tongda Wu, Keni Qiu, Huazhong Yang, Yongpan Liu:
Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support. 339-344 - Mubashir Hussain, Amin Malekpour, Hui Guo, Sri Parameswaran:
EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip. 345-350 - Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. 351-356 - Marjan Asadinia, Christophe Bobda:
Enhancing Lifetime of PCM-Based Main Memory with Efficient Recovery of Stuck-at Faults. 357-362
Student Research Forum
- David Berend, Bernhard Jungk, Shivam Bhasin:
Guessing Your PIN Right: Unlocking Smartphones with Publicly Available Sensor Data. 363-368 - Debjyoti Bhattacharjee, Anupam Chattopadhyay:
Synthesis, Technology Mapping and Optimization for Emerging Technologies. 369-374 - Saeideh Shirinzadeh, Rolf Drechsler:
Logic Synthesis for In-memory Computing Using Resistive Memories. 375-380 - Debapriya Basu Roy, Debdeep Mukhopadhyay:
Minimalistic Perspective to Public Key Implementations on FPGA. 381-386 - Shin Miyamoto, Nobuaki Kobayashi:
Development of High-Stability, Low-Leakage 6Tr-SRAM with Single Data Line and Single Power Supply Using SOTB Process. 387-392 - Zhiming Zhang, Qiaoyan Yu:
Exploiting Principle of Moving Target Defense to Secure FPGA Systems. 393-398
Session 08: System Design and Security III
- Faqiang Mei, Lei Zhang, Chongyan Gu, Yuan Cao, Chenghua Wang, Weiqiang Liu:
A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA. 399-404 - Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan:
LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. 405-410 - Atul Prasad Deb Nath, Swarup Bhunia, Sandip Ray:
ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies. 411-416
Session 09: Computer Aided Design and Verification II
- Yongfu Li, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong:
Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching. 417-422 - Antara Ain, Akshay Mambakam, Pallab Dasgupta:
Feature Based Coverage Analysis of AMS Circuits. 423-428 - Ryutaro Doi, Masanori Hashimoto:
SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA. 429-434
Session 10: Emerging and Post-CMOS Technologies II
- Kaiyuan Guo, Jincheng Yu, Xuefei Ning, Yiming Hu, Yu Wang, Huazhong Yang:
RRAM Based Buffer Design for Energy Efficient CNN Accelerator. 435-440 - Sagarvarma Sayyaparaju, Ryan Weiss, Garrett S. Rose:
A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic Systems. 441-446 - Nicholas Jao, Akshay Krishna Ramanathan, Srivatsa Rangachar Srinivasa, Sumitha George, John Sampson, Vijaykrishnan Narayanan:
Harnessing Emerging Technology for Compute-in-Memory Support. 447-452
Session 11: Analog and Mixed Signal II
- M. K. Jayaram Reddy, Sreenivasulu Polineni, Laxminidhi Tonse:
91dB Dynamic Range 9.5nW Low Pass Filter for Bio-Medical Applications. 453-457 - Luca Marchetti, Yngvar Berg, Mehdi Azadmehr:
A Low Power, High Gain Semi-Floating Gate Amplifier for Resonating Sensors Front-End. 458-463 - Ankit Rehani, Sujay Deb, Pydi Ganga Bahubalindruni, Bhavin Odedara, Srikanth Bojja:
A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency Scaling. 464-469
Session 12: System Design and Security IV
- Chenchen Liu, Qide Dong, Fuxun Yu, Xiang Chen:
ReRise: An Adversarial Example Restoration System for Neuromorphic Computing Security. 470-475 - Chang Song, Hsin-Pai Cheng, Huanrui Yang, Sicheng Li, Chunpeng Wu, Qing Wu, Yiran Chen, Hai Li:
MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks. 476-481 - Wenshuo Li, Jincheng Yu, Xuefei Ning, Pengjun Wang, Qi Wei, Yu Wang, Huazhong Yang:
Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks. 482-487
Special Session 03: Essential Keys to Manufacturability: Layout Features and Lithography Technologies
- Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li, Xuan Zeng:
Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach. 488-493 - Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang:
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. 494-497 - Iris Hui-Ru Jiang, Hua-Yu Chang:
Recent Research and Challenges in Multiple Patterning Layout Decomposition. 498-499 - Shao-Yun Fang, Kuo-Hao Wu:
Guiding Template-Induced Design Challenges in DSA-MP Lithography. 500-502
Session 13: Digital Circuits and FPGA Based Designs II
- Yizhi Wang, Jun Lin, Zhongfeng Wang:
FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks. 503-508 - Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini:
Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes. 509-515 - Fangxuan Sun, Jun Lin, Zhongfeng Wang:
An Optimized Architecture For Decomposed Convolutional Neural Networks. 516-521 - Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu:
Interconnect Delay Analysis for RRAM Crossbar Based FPGA. 522-527
Special Session 04: Emerging Trends in Energy Efficient and Secure Neural Network Acceleration
- Tao Liu, Zihao Liu, Qi Liu, Wujie Wen:
Enhancing the Robustness of Deep Neural Networks from "Smart" Compression. 528-532 - Zhezhi He, Shaahin Angizi, Deliang Fan:
Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM. 533-538 - Sai Li, Wang Kang, Xing Chen, Jinyu Bai, Biao Pan, Youguang Zhang, Weisheng Zhao:
Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions. 539-544
Session 14: System Design and Security V
- Nan Wang, Manting Yao, Dongxu Jiang, Song Chen, Yu Zhu:
Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints. 545-550 - George Provelengios, Arman Pouraghily, Russell Tessier, Tilman Wolf:
A Hardware Monitor to Protect Linux System Calls. 551-556 - Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler:
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. 557-562
Session 15: Digital Circuits and FPGA Based Designs III
- Chenghong Wang, Zeinab S. Jalali, Caiwen Ding, Yanzhi Wang, Sucheta Soundarajan:
A Fast and Effective Memristor-Based Method for Finding Approximate Eigenvalues and Eigenvectors of Non-negative Matrices. 563-568 - Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, Toshinori Sato:
A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing. 569-574 - Pengfei Huang, Chenghua Wang, Ruizhe Ma, Weiqiang Liu, Fabrizio Lombardi:
A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering. 575-580
Special Session 05: Intelligent Methods & Techniques for Reliable and Adaptive Multicore/Manycore System
- Florian Kriebel, Semeen Rehman, Muhammad Abdullah Hanif, Faiq Khalid, Muhammad Shafique:
Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine Learning. 581-586 - Luca Stornaiuolo, Marco D. Santambrogio, Donatella Sciuto:
On How to Efficiently Implement Deep Learning Algorithms on PYNQ Platform. 587-590 - Sri Harsha Gade, Mitali Sinha, Sidhartha Sankar Rout, Sujay Deb:
Enabling Reliable High Throughput On-chip Wireless Communication for Many Core Architectures. 591-596
Session 16: Testing, Reliability, and Fault-Tolerance II
- Nishchay H. Sule, Troy Powell, Sameer Hemmady, Payman Zarkesh-Ha:
Predicting the Tolerance of Extreme Electromagnetic Interference on MOSFETs. 597-601 - Yuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng:
Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors. 602-607 - Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha:
Performance Enhancement of Split Length Compensated Operational Amplifiers. 608-613
Session 17: System Design and Security VI
- James Shey, Naghmeh Karimi, Ryan W. Robucci, Chintan Patel:
Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy. 614-619 - Prasanna Ravi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay:
PPAP and iPPAP: PLL-Based Protection Against Physical Attacks. 620-625 - Ahmad Patooghy, Ehsan Aerabi, Hamidreza Rezaei, Miguel Mark, Mahdi Fazeli, Michel A. Kinsy:
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method. 626-631
Session 18: Digital Circuits and FPGA Based Designs IV
- Suman Adhepalli Muralikrishnan, Pulkit Sapra, Saurabh Agrawal, Piyush Chanana, M. Balakrishnan, P. V. M. Rao:
FPGA-Based Controllers for Compact Low Power Refreshable Braille Display. 632-637 - Yu Zou, Mingjie Lin:
Very Large-Scale and Node-Heavy Graph Analytics with Heterogeneous FPGA+CPU Computing Platform. 638-643 - SreeCharan Gundabolu, Xiaofang Wang:
On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded Systems. 644-649
Special Session 06: Large Scale Integration (mVLSI): Recent Developments and Upcoming Challenges
- Tsung-Yi Ho:
Design Automation and Test for Flow-Based Biochips: Past Successes and Future Challenges. 650-654 - Yung-Chun Lei, Tien-Kuo Lin, Juinn-Dar Huang:
Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips. 655-659 - Weiqing Ji, Tsung-Yi Ho, Hailong Yao:
More Effective Randomly-Designed Microfluidics. 660-665 - Junchao Wang, Lingxuan Fu, Liyang Yu, Xiwei Huang, Philip Brisk, William H. Grover:
Accelerating Simulation of Particle Trajectories in Microfluidic Devices by Constructing a Cloud Database. 666-671
Special Session 07: Secure Hardware Design for Distributed Agents
- Sudeendra Kumar K, Saurabh Seth, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamalakanta Mahapatra:
PUF-Based Secure Test Wrapper for SoC Testing. 672-677 - Pranav Dharmadhikari, Akhilesh Raju, Ranga Vemuri:
Detection of Sequential Trojans in Embedded System Designs Without Scan Chains. 678-683 - Mike Borowczak, Rafer Cooley, Shaya Wolf:
Designing for Security Within and Between IoT Devices. 684-689 - Prasanna Kansakar, Arslan Munir:
A Two-Tiered Heterogeneous and Reconfigurable Application Processor for Future Internet of Things. 690-696
Special Session 08: Embedded Multi-Core in Automotive and I4.0
Special Session 09: Energy Efficient and Hardware Secured Architectures for Smart Electronics I
- S. Dinesh Kumar, Carson Labrado, Riasad Badhan, Himanshu Thapliyal, Vijay Singh:
Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices. 697-702 - Hui Zhao, Xianwei Cheng, Saraju P. Mohanty, Juan Fang:
Designing Scalable Hybrid Wireless NoC for GPGPUs. 703-708 - Anirban Sengupta, Saraju P. Mohanty:
Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption. 709-713
Special Session 10: Timing in the Nanometer Era
- Iris Hui-Ru Jiang, Pei-Yu Lee:
Timing Macro Modeling for Efficient Hierarchical Timing Analysis. 714 - Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. 715-718
Special Session 11: Attacking Dynamic Optimizations in the Era of Complex Heterogeneous Multi-core Computing I
- Islam Badreldin, Ann Gordon-Ross, Tosiron Adegbija, Mohamad Hammam Alsafrjalani:
Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges. 719-725 - Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Anupam Chattopadhyay:
An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning. 726-731
Special Session 12: Energy Efficient and Hardware Secured Architectures for Smart Electronics II
- Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar:
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation. 732-737 - Manoj Kumar JYV, Ayas Kanta Swain, Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Kamalakanta Mahapatra:
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip. 738-743 - Juan Fang, Zeqing Chang, Yanjin Cheng, Hui Zhao:
Exploration on Routing Configuration of HNoC with Reasonable Energy Consumption. 744-749
Special Session 13: Design Using Emerging Devices
- Xueqing Li, Longqiang Lai:
Nonvolatile Memory and Computing Using Emerging Ferroelectric Transistors. 750-755
Special Session 14: Attacking Dynamic Optimizations in the Era of Complex Heterogeneous Multi-core Computing II
- Siqi Wang, Alok Prakash, Tulika Mitra:
Software Support for Heterogeneous Computing. 756-762 - Kenneth O'Neal, Philip Brisk:
Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey. 763-768
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